| 摘要 |
<p>PURPOSE:To prevent a warning from being generated in a standby system and to confirm the normality of the standby system by providing bit buffer circuits, which absorb the PLO normal phase error of respective common processing parts, in a channel corresponding part. CONSTITUTION:A channel processing part 2 is equipped with buffer circuits 5a and 5b. Duplexed common processing parts 1a and 1b respectively generate clock signals 11a and 11b from respective PLO circuits 4 and distribute the signals to a channel corresponding part 2a. On the other hand, the channel corresponding part 2a selects either the clock signal 11a or 11b by a selecting circuit 3 and outputs a selected clock signal 12. A data signal 13 of the channel corresponding part 2 is written to the bit buffer circuits 5a and 5b by the selected clock signal 12, read by the clock signals 11a and 11b from the respective common processing parts 1a and 1b afterwards and distributed to the respective common processing parts 1a and 1b. Thus, the data signal is normally inputted to the respective common processing parts 1a and 1b by the clock signals and the warning the prevented from being generated in the standby system.</p> |
