| 摘要 |
PURPOSE:To decrease a charge/discharge current and a through-current and to reduce the power consumption by adding a gate controlling a product term line from an AND plane while giving an optional delay to a precharge clock. CONSTITUTION:A gate is provided, which controls a product term line from an AND plane while giving an optional delay to a precharge clock. That is, AND circuits 13-15 are controlled with a precharge clock PC via a delay gate 1 and a signal from a product term line from an AND plane being an input to an OR plane and the OR plane is synchronized with the AND plane. Thus, a dynamic programmable logic array saving the power consumption is obtained. |
