发明名称 GATE ARRAY PROVIDED WITH MEMORY
摘要 <p>PURPOSE:To reduce an interconnection region between a region exclusively used for a memory and a logic part by a method wherein logic parts are formed on both sides of the region exclusively used for the memory, one logic part contains a gate having a capacitance required to constitute an input-side logic circuit and the other logic part contains a gate of a capacity required to constitute an output-side logic circuit. CONSTITUTION:Logic parts 14, 18 where transistor basic circuits have been arranged regularly are formed on both sides of a region 12 exclusively used for a memory. One logic part 14 contains at least a gate having a capacitance required to constitute an input-side logic circuit of the region 12 exclusively used for the memory; the other logic part 18 contains at least a gate of a capacity required to constitute an outer-side logic circuit of the region 12 exclusively used for the memory. Thereby, interconnection regions 16, 20 between the region 12 exclusively used for the memory and the logic circuits 14, 18 can be reduced.</p>
申请公布号 JPH0329363(A) 申请公布日期 1991.02.07
申请号 JP19890165047 申请日期 1989.06.26
申请人 RICOH CO LTD 发明人 SAKAMOTO KAZUHO;FUJII TATSUYA;TANAKA MASABUMI
分类号 G11C17/00;G11C11/41;H01L21/82;H01L27/10;H01L27/118 主分类号 G11C17/00
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