| 摘要 |
<p>PURPOSE:To minimize the delay time of a PCM circuit by realizing a predioclonus circuit preventing a multi-frame slip only with a buffer capacity performing frame synchronization protection. CONSTITUTION:A frame synchronization is acquired from an input PCM signal in a frame synchronizing circuit 101 and a frame synchronizing signal 10 is fed to a 1st address counter 200. A clock extraction circuit 102 extracts a bit clock from the inputted PCM signal and supplies a clock 11 to a counter 200. The output 12 of the counter 200 is used as the write address of a RAM 100 and the input PCM data is written according to the address. A clock generator 400 supplies the clock R23 to a 2nd address counter 202 and a multi-frame synchronization circuit 500. The counter 202 generates the readout address 20 of the RAM 100 according to the clock R23. According to the readout address 20, the data of the RAM 100 is read and given to an output terminal 2 and the synchronous circuit 500.</p> |
