| 摘要 |
<p>Disclosed is a data bus synchronizer circuit (20) based on the principle that if the phase relationship of a sending bus clock (22) and a receiving bus clock (24) is known at a first point in time, and the frequencies of the two clocks are known and fixed, then the phase relationship can be determined at any time in the future through extrapolation. The circuit has a metastabilization pipe (50), used to remove metastability from the sending bus clock, comprising a plurality of flip-flop circuits connected in series. The clock of the sending bus is input to the first flip-flop of the pipe, and the pipe flip-flop circuits are clocked by the receiving bus clock. Because the extrapolation principle, the metastabilization pipe can be arbitrarily long. Output of this pipe is fed to the input of a serial to parallel conversion circuit (54) comprising a second group of flip-flop circuits connected in series, and clocked by the receiving bus clock. The parallel outputs of the converter are fed to selector circuits (56, 58), with the desired adjacent parallel outputs being selected by programming bits (60) which allow the circuit to be adapted to varying ratios of sending and receiving clock speeds. The outputs of the selector circuits are fed to an AND gate (62) that creates an enabling signal that is used to enable the transfer. The circuit allows a transfer even where one of the bus cycles is more than twice as long as the other bus cycle, and the circuit takes advantage of bus setup time to speed up data transfers.</p> |
