| 摘要 |
<p>The EEPROM memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series on the source and is controlled by the transfer terminal.</p> |
