| 摘要 |
PURPOSE:To realize a comparatively small-scale and high-speed multiplication remainder computing element by storing a numerical value alpha1 of (n+1)-bit as a cummulative value, making the N of a final cumulative value into a divisor and obtaining a remainder value through the use of an adder, a switching device, etc. CONSTITUTION:An alpha0 to be finally obtained to the output of an adder 103 by repeating an operation to store the cumulative value alpha1 obtained from the adder 103 into a cumulative value register 101 l times each time a digit alpha1 is supplied to a memory 102 for each one bit from a highest order degit alpha1-1 of A sequently towards a low order side is made equivalent to [A.B]modN in an algebraic system made into the N divisor. consequently, when alpha0 is obtained, by finally executing a correcting operation to highly subtract 3N from alpha0 by using a remainder computing element 104, the [A.B]modN made into the goal is obtained. In such a way, since a realization can be executed by each one memory, adder and register, a circuit scale is comparatively small. An equal or faster processing speed can be achieved. |
