发明名称 CPU RESETTING SYSTEM FOR CONTROLLER TO BE SUPERVISED
摘要 <p>PURPOSE:To reset a controller to be supervised by sharing a communication transmission line by switching and outputting the reset signal of a pattern decided in advance not existing in an normal operation instead of a transmission signal from a supervisory control part for master station. CONSTITUTION:When the occurrence of abnormality in the controller 12 to be supervised is conjectured and a switch 21 is operated, a switch 23 is switched and connected from a transmission/reception part 15 to a reset pattern generator 20 side via a switch control part 22, and the reset signal of the pattern decided in advance not existing in the normal operation of a signal to be transmitted is sent to the controller 12 to be supervised via the switch 23 and a transmission line 13. A reset pattern detector 24, when detecting the reset signal, outputs a detected signal to a reset control part 25, and resets a CPU in a supervisory controller 18 for slave station compulsorily. In such a way, the controller 12 to be supervised can be reset by sharing the communication transmission line between the supervisory controller 11 and the controller 12 to be supervised.</p>
申请公布号 JPH0326096(A) 申请公布日期 1991.02.04
申请号 JP19890160173 申请日期 1989.06.22
申请人 FUJITSU LTD 发明人 SHINOZAKI YUTAKA
分类号 G06F1/24;H04Q9/00 主分类号 G06F1/24
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