| 摘要 |
<p>PURPOSE:To obtain a stable reception clock with little jitter by performing phase comparison with a PLL circuit by using output corresponding to a center zero cross point i one cycle of an amplitude phase modulation signal after discriminating connection polarity. CONSTITUTION:The system is equipped with an amplitude limiting amplifier 30 to convert the amplitude phase modulation signal with data clock frequency to a logic level signal, a zero cross detection circuit 26 to generate the output at the rise and fall of the logic level signal, a window gate circuit 31 to select the passage of either the output corresponding to the center zero cross point in one cycle of the amplitude phase modulation signal or all the output out of the output of the zero cross detection circuit 26, and a PLL circuit 32 to compare the output of the zero cross detection circuit 26 in the neighborhood of the frequency of integer times the clock frequency or in the neighborhood of the same frequency synchronizing with the switching of the window gate circuit 31. The reception clock is generated by detecting the center zero cross point in one cycle of the amplitude phase modulation signal after the connection polarity is discriminated. In such a way, the stable reception clock with little jitter can be obtained.</p> |
