发明名称 PACKET TRANSFER SYSTEM
摘要 PURPOSE:To transfer packets with a simple control without enlarging the hardware scale by reading out stored packets from a dual port memory based on a packet transfer request independently of the write operation. CONSTITUTION:A dual port memory 22 has two systems of ports of data input and output terminals and an address signal input terminal and can be accessed from both ports independently of each other. Consequently, packets stored in the dual port memory 22 can be read out by a read control means 24 even while packets are written in the dual port memory 22 by a write control means 23. Thus, it is unnecessary to adjust the timing between the write side and the read side of the dual port memory 22, and it is unnecessary to pay attention to the switching timing on the read side.
申请公布号 JPH0324844(A) 申请公布日期 1991.02.01
申请号 JP19890158636 申请日期 1989.06.21
申请人 FUJITSU LTD 发明人 HAZAMA HISAMICHI
分类号 H04L12/56 主分类号 H04L12/56
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