| 摘要 |
PURPOSE:To reduce the number of logical elements and to shorten a conversion processing time by using inversion circuits for outputting exclusive OR and all '1' detecting circuits for outputting AND values for execute conversion without using an adder. CONSTITUTION:A signal '1111' indicating '-1' by the display of 2's comple ment is inputted to the uppermost terminal 4. Signals outputted from the terminals Y of inversion circuits 11 to 13 are '0'. An all '1' detecting circuit 41 outputs the OR of the same signals. All '1' detecting circuits 42, 43 respective ly receive the outputs of the terminal 4 and the inversion circuit 11 and the Y terminals of the inversion circuits 11, 12 and signals '1', '0', '0' are respec tively outputted from the outputs of detecting circuits 41 to 43. Inversion circuits 51 to 53 receive the outputs of the circuits 41 to 43 by their I terminals and the outputs of the circuits 11, 12 by their D terminals and a signal '1001', i.e. a signal indicating '-1' by the display of an absolute value appears from each of output terminals 31 to 34 to convert a 2's complement display signal into absolute value display. Even when a signal '1001' indicating '-1' by the display of an absolute value is inputted to the terminals 1 to 4, signals '1111' similarly appear from the terminals 31 to 34 execute signal conversion. |
