发明名称 WORD LINE DRIVING CIRCUIT FOR DYNAMIC RAM
摘要 PURPOSE:To reduce the gate width of a MOS transistor TR for transfer gate, to reduce the capacity of a boosting capacitor, and to increase the access speed by constituting a transfer gate of the n-channel MOS TR formed in a private p-type well separated from other circuit elements and applying a positive potential to the p-type well at the time of electric charge transfer. CONSTITUTION:The transfer gate consists of an n-channel MOS TR Q2 formed in a private p-type well 12 separated from other circuit elements, and a positive potential is applied to the p-type well 12 at the time of electric charge transfer. Since the positive potential is given to the p-type well 12 of the n-channel MOS TR Q2 constituting the transfer gate at the time of transferring the electric charge of a boosting circuit, the rise of the threshold and the reduction of the current due to the back gate bias effect are suppressed. When the transfer gate is turned off, the potential of the p-type well 12 is set to 2V or lower to secure a satisfactory cut-off characteristic. Thus, the access speed is increased, and the gate width of the MOS TR for transfer gate is reduced, and the capacity of the boosting capacitor is reduced.
申请公布号 JPH0323591(A) 申请公布日期 1991.01.31
申请号 JP19890157158 申请日期 1989.06.20
申请人 TOSHIBA CORP 发明人 OWAKI YUKITO;TSUCHIDA KENJI
分类号 G11C11/407;G11C11/408;H01L21/8242;H01L27/10;H01L27/108 主分类号 G11C11/407
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