| 摘要 |
PURPOSE:To improve speed for arithmetic by defining the complement output of a register composed of a synchronous RAM, as the input of an arithmetic part and making timing for precharge and sampling hold same for the register and arithmetic part. CONSTITUTION:A dynamic arithmetic unit is provided with a register 1 composed of the synchronous RAM to accompany the precharge and sampling hold in read circuit operation and an arithmetic circuit 2 to be controlled the execution of the arithmetic at the timing for the precharge and sampling hold. Phase matching is executed so that the level of the register 1 at the precharge time of a digit line is the inactive level of a sampling circuit in the arithmetic circuit 2. Then, the signal is directly connected to the sampling circuit and the register 1 and arithmetic circuit 2 are operated at the same timing for the precharge and sampling hold. Thus, processing is executed at hight speed from the precharge of the resister 1 to the prossession of an output Sm from the arithmetic part 2 and a hardware is simplified. |
