发明名称 |
Semiconductor integrated circuit. |
摘要 |
<p>There is disclosed a semiconductor integrated circuit provided with an input circuit including an N-channel MOS transistor (N2) of which threshold voltage is set to a value lower than those of N-channel MOS transistors (N1, N3, N4) constituting other internal circuits of the integrated circuit. Thus, a circuit having a high operating margin for power supply noises is provided. This circuit further comprises a P-channel MOS transistor (P2) constituting a portion of a NOR gate or a NAND gate together with the above-mentioned N-channel MOS transistor (N2).</p> |
申请公布号 |
EP0410473(A2) |
申请公布日期 |
1991.01.30 |
申请号 |
EP19900114459 |
申请日期 |
1990.07.27 |
申请人 |
KABUSHIKI KAISHA TOSHIBA;TOSHIBA MICRO-ELECTRONICS CORPORATION |
发明人 |
KATO, HIDEO;KIKUCHI, SHINICHI;NAKAI, HIROTO;IWAHASHI, HIROSHI |
分类号 |
H03K19/0185;H03K19/003;H03K19/0948 |
主分类号 |
H03K19/0185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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