发明名称 Method and apparatus for preventing failure of a CPU.
摘要 <p>Disclosed are a method and apparatus for preventing runaway of CPU using a battery voltage as a power source voltage, in which the operation of CPU and the power source voltage of CPU are inspected at the abnormal operation of CPU and/or at the abnormal reduction of the power source voltage of CPU, system resetting is effected on CPU, system reset signals for CPU are counted, and when the count number of system reset signals for a predetermined time satisfies predetermined conditions, it is judged that CPU is in failure, and when the abnormal reduction of the power source voltage of CPU is detected, the counting of system reset signals is prohibited.</p>
申请公布号 EP0410030(A1) 申请公布日期 1991.01.30
申请号 EP19890113690 申请日期 1989.07.25
申请人 JAPAN ELECTRONIC CONTROL SYSTEMS CO., LTD. 发明人 GOKAN, YOSHIAKI C/O JAPAN ELECTRONIC CONTROL;AKAISHI, SHIGERU C/O JAPAN ELECTRONIC CONTROL
分类号 G06F11/00;G06F11/14 主分类号 G06F11/00
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