Graphics display split-serial register system.

摘要

A graphical data presentation circuit and method which allows for tightly packing a video memory (130) without regard for the pixel size or number of pixels on a line of the graphic display. The memory output split-serial register (140) is used together with a counter (94) to maintain count of the currently executing output stage of the register (140). When a first half of the register (140) has completed transferring its data to the display it is cleared and reloaded with the first part of the next memory row. When the second half of the register (140) is likewise finished transferring its data it is also cleared and reloaded with the data from the second half of the memory row. This alternating operation allows for mid-row register refreshing without affecting data transfer performance.