发明名称 EVENT QUALIFICATION TEST ARCHITECTURE OF INTEGRATED CIRCUIT
摘要 PURPOSE: To execute a boundary test in an operation mode of an IC, by storing and logically operating arriving data by a logic circuit connected between an input and an output circuits of the IC, and comparing the data with estimation data. CONSTITUTION: Arriving data are stored, logically operated, etc., by a logic circuit connected between a data input D0-7 and a data output Q0-7 of an IC. The data are analyzed and stored by an input and an output test registers(TCR) 12, 22 when a predetermined state is detected. At this time, the predetermined state can be detected by comparing data from the logic circuit with a stored estimation data word. On the occasion of a boundary test, test data are shifted into a test circuit of the TCR 22 under the control from a test port 48. An event recognition module 30 generates a control in accordance with an input of the predetermined state via a CTERM signal, and outputs a test pattern to the output Q0-7. Accordingly, data passing a boundary of the IC can be dynamically observed.
申请公布号 JPH0320683(A) 申请公布日期 1991.01.29
申请号 JP19900029369 申请日期 1990.02.08
申请人 TEXAS INSTR INC <TI> 发明人 RII DEII UIITSUERU
分类号 G01R31/28;B42D15/00;G01R31/317;G01R31/3185;G06F11/22;H01L21/66;H01L21/822;H01L27/04 主分类号 G01R31/28
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