发明名称 ROM CONTROL SYSTEM
摘要 <p>PURPOSE:To make the CPU 1 refer to the block data in an ROM with one instruction only and to relieve the burden in a CPU, by read out consecutive block data by only transmitting a start address to the ROM. CONSTITUTION:A start address of an ROM 3 is transmitted on an address line 17 in the form of a parallel data from a microcomputer 9 and transmitted on an address line 18 in the form of serial data. The readout operation of an ROM data is started from the address outputted from an address counter 13. An address register 15 is added with an adder/subtractor 16. The address of the ROM 3 is renewed by every +1 or -1, allowing the ROM 3 to continuously pick up data. Thus, since the computer 9 transmits the start address only, the burden can be relieved.</p>
申请公布号 JPS57179980(A) 申请公布日期 1982.11.05
申请号 JP19810062474 申请日期 1981.04.27
申请人 HITACHI SEISAKUSHO KK 发明人 NOMIYA HIROYASU;SHIYUUTOU KIMIYOSHI;HARA HIDEO
分类号 G11C17/00;G06F12/02;G11C8/04 主分类号 G11C17/00
代理机构 代理人
主权项
地址