| 摘要 |
A microcomputer is disclosed which provides for a dedicated DMA data and address bus connecting an on-chip DNA controller with on-chip memories, and with on-chip ports for access to external memory and input/output devices. The DMA controller contains a control register which has two start bits, capable of representing four start codes. The four start codes allow for the unconditional starting and aborting of a DMA transfer, as well as for stopping the DMA after the current read or write operation, or after the next write operation (i.e., completion of a data word transfer). The control register also contains two status bits which the DMA controller writes with the status of the DMA operation, and also contains two synchronization bits for synchronizing the DMA operation in the source, destination, or source and destination modes (or not at all). Two interrupt enable registers are provided in the microcomputer, for independently enabling interrupts for the CPU and the DMA. In any of the synchronization modes, the DMA will suspend its operation awaiting an interrupt which is not enabled for the CPU but which is enabled for purposes of DMA. The use of system interrupts for DMA synchronization does not require dedicated DMA interrupt terminals for the microcomputer.
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