| 摘要 |
PURPOSE: To suppress a high current, to reduce current consumption and to improve voltage stability by providing a clamp circuit having a P-channel transistor(TR) and an N-channel TR with 1st to 3rd inverters and designing the 1st to 3rd inverters so as to have respectively different switching points. CONSTITUTION: A P-channel field effect transistor(FET) TP1 is connected between a terminal VDD and an I/O terminal N1 and an N-channel FET TN1 is connected between the I/O terminal N1 and a potential reference point such as ground. The input of an inverter 11 is connected to the node N1, the output of an inverter 12 is connected to the control electrode of the FET TP1 through a node N2 and the output of the inverter 11 is connected to the input of the inverter 12 through a node N3. The switching point of the 1st inverter 11 is designed so as to be sharply different from the switching voltage or input voltage of the 3rd inverter 13. Consequently a high current can be suppressed, voltage stability can be improved and power consumption can be reduced. |
