| 摘要 |
<p>PURPOSE:To reduce the waste of operating speed by feeding back the output signal of an internal reference signal generation circuit in an asynchronous type memory to an input side. CONSTITUTION:When skew occurs in input signals A, B and C such as an address signal, a chip select signal, etc., the rise/fall of the output of the internal reference signal generation circuit is fed back to the input side via a delay circuit 2 with a level change detection signal from the level change detection circuit 1 for a signal changing first. The level change detection signal from the input signal having negligible inter-signal skew can be neglected by feedback to the circuit 2, and the fall of the output signal of the internal reference signal generation circuit can be performed. Therefore, the operation of a memory can be started from the trailing edge of the output signal from the internal reference signal generation circuit, which accelerates the operating speed.</p> |
