| 摘要 |
PURPOSE: To reduce phase jitter without increasing the requirement for the precision of a D/A converter by connecting a fractioner forming a principal value and a residual value to the post stage of a digital loop filter and supplying a sum consisting of a correction bit led from the principal value and the residual value to the D/A converter. CONSTITUTION: The phase adjusting circuit is provided with a phase comparator (PD), an A/D converter(ADC), a digital lop filter(LF) a D/A converter(DAC), and a voltage controlled oscillator(VCO) and a fractioner (FR) forming a principal value (HW) and a residual value (RW) is connected to the post stage of the LF of which timing is controlled by a 1st clock (TL). A sum consisting of a correction bit (KB) led from the HW and the RW is supplied to the DAC of which timing is controlled by a 2nd clock (TA). The KB corresponds to one bit of correction bits (KW) supplied to a shift register(SR) and read out from the SR by the TA. |
