| 摘要 |
PURPOSE:To reduce the power consumption for a superheterodyne receiver, by periodically giving power to a PLL frequency synthesizer at reception waiting and energizing other circuit for a prescribed time only in a locking state. CONSTITUTION:At reception waiting, a synthesizer SYN controlling circuit 27 conducts a switch 26 only during the period W1 in a period W, power is supplied to a PLL frequency SYN3 and a lock detecting circuit 28 from a DC power supply 17 and interrupts the switch 26 during the period of W2. The SYN3 is attained to locking state after a lock-in time TR after the conduction of the switch 26. When the circuit 28 detects this state, the detection circuit controls a reception controlling circuit 19, which conducts a switch 18 for the reception time W3 and supplies power to other circuits and the reception is possible for the time W3. After the time W3, the circuit 19 interrupts the switch 18 and a circuit 27 interrupts the switch 26. When a callout signal is generated from other communication device in time t0, the switches 18 and 26 remain conductive in the timing just after and the call can be made. |
