| 摘要 |
PURPOSE:To attain delicate picture magnification reduction processing by adding a magnification factor by an n-bit adder, using the (n+1)th bit of the result of addition as a carry, latching the result, discriminating valid or invalid picture element data and addition based on the carry thereby magnifying and reducing the picture. CONSTITUTION:An n-bit adder 2 adds a magnification data m and a low-order n-bit data DL and outputs the result of calculation to a latch 3. The latch 3 latches (n+1) bits, feeds back the low-order n-bit data DL to the n-bit adder 2 to output the most significant (n+1)th bit to a picture data correction section 4 as a carry. Then the picture data correction section 4 discriminates valid/ invalid/addition state of an input picture data DA based on a magnification/ reduction data P and a carry C and applies picture processing of the input picture data DA to output an output picture data DO. Thus, picture magnification reduction processing with a delicate magnification factor is implemented with the hardware quickly. |
