发明名称 |
WAFER-SCALE-INTEGRATED ASSEMBLY |
摘要 |
The standard silicon wafer of a conventional wafer-scale-integrated assembly is doped to render it highly conductive. Additionally, a conductive layer is formed on the bottom of the wafer. The bottom-side layer forms an easily accessible ground plane of the assembly. Moreover, this layer and the conductive silicon constitute one plate of an advantageous wafer-size decoupling capacitor. A nearly continuous power layer and a relatively thick layer of silicon dioxide on the top side of the assembly form the other elements of the decoupling capacitor. Additionally, the nearly continuous power layer constitutes an effective a-c ground plane for overlying signal lines. |
申请公布号 |
EP0197089(B1) |
申请公布日期 |
1991.01.23 |
申请号 |
EP19850904950 |
申请日期 |
1985.09.30 |
申请人 |
AMERICAN TELEPHONE AND TELEGRAPH COMPANY |
发明人 |
HERRERO, VICTOR;SCHAPER, LEONARD, WILLIAM |
分类号 |
H01L23/52;H01L23/14;H01L23/538;H01L23/64 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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