Phase locked loop for the extraction of a clock signal for data transmission systems.

摘要

Circuit for the extraction of a clock signal from a random data signal. The circuit comprises a PLL with an adaptive phase discriminator which adapts the clock signal to the random data signal in order to have a signal devoid of asymmetric characteristics, causing transients, at the discriminator output. The adaptive phase discriminator comprises two edge detectors, two flip-flops and four logic gates.