| 摘要 |
An interrupt control circuit is configured as a memory circuit to output interrupt vector information in response to multilevel interrupt requests for a CPU. The interrupt control circuit is provided with a plurality of interrupt vector generators configured as a memory matrix array. Each interrupt vector generator effects self-addressing based on the contents of a memory cell functioning as a latch circuit in which is stored an interrupt request and the contents of a memory cell functioning as a mask register in which interrupt control information is stored. The interrupt control circuit is further provided with a single output buffer commonly coupled to memory cells constituting each interrupt vector generator, thereby providing access to a self-addressed interrupt vector generator to concurrently output the interrupt vector information from the respective memory cells to a data bus via the single output buffer. A small-sized interrupt control circuit having a high signal transmission speed is thereby provided.
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