| 摘要 |
<p>PURPOSE:To improve transmission efficiency in packet communication, etc., by counting the number fo effective data and applying the number as an additional bit. CONSTITUTION:A sampling circuit 2 restores an asynchronizing signal, excludes a start bit or stop bit which are redundant bits, sends only the effective data to a FIFO memory 5 and applies 1 signal, which shows the position of the effective data, to the FIFO memory 5 or an asynchronous side counter circuit 3. The asynchronous counter circuit 3 counts the number of the signals and presets the number of the effective data to a synchronous side counter circuit 6. Next, data to be limited to the number of the effective data, which is preset to the synchronous side counter circuit 6, are read from the FIFO memory 5 and gathered as a packet signal. Then, a result counted by the synchronous side counter circuit 6 is multiplexed to a main signal by a multiplexing circuit 8. Thus, redundant data are removed and the transmission efficiency can be improved.</p> |
