| 摘要 |
Disclosed is a mode selecting circuit for semiconductor memory device having one or more mode selection signal generating means. Each mode selection signal generating means consists of an inverter means for inverting a reset signal; a mode selector using connecting means between a first power source terminal and a node coupled with the output terminal of the inverter and formed during the manufacturing process; a first latch for latching a low or high signal depending on the circumstance; an output buffer; and a reset signal generator for generating reset signals in synchronization with the leading edge of a chip enable signal, and for delivering the reset signals to the respective mode selection signal generator. The circuit according to the present invention is simple and convenient in design, thereby shortening the turn around time of the memory device. Further, it promises exact and correct circuit operations, and makes it possible to reduce the manufacturing cost. The manufacturer can also furnish diversified options in order to meet the requirements of users.
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