| 摘要 |
The circuit has a digital sum generating circuit (1) including a ROM(ROM1) for generating 10-bit code word signal by a clock signal (CLK2), a parity generator (PG1) for generating parity code, a PTS converter (PTSC1) for converting output data of the ROM to series data by a control signal (CS2)and a clock signal (CLK3), a NRZI converter (NRZIC1) for NRIT converting of output signal of the PTSC1 by clock signal passed through an EXOR gate, a binary up down counter (BVDC1) for counting the output signal of the NRZI converter utilizing clock signal passed through an EXOR gate (EXOR1), and a comparator (COMP2) for comparing output signal of the counter with reference signal.
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