发明名称
摘要 <p>PURPOSE:To realize high-speed frame retrieval, etc., of a video signal, by recording an address signal in the interval of horizontal synchronizing signal. CONSTITUTION:A pulse generator 8 separates a synchronizing signal from an input signal and supplies the synchronizing signal to a timing signal generation circuit 9. The circuit 9 controls an RAM11 and outputs an address and a digital signals having a fixed pattern to the synchronizing signal part of the video signal. These signals are encoded in a coding circuit 12, inputted to a signal adder 5 via a switch S1 to be added to a frequency-converted chromaticity signal, and recorded in a proper memory medium. The address signal recorded in the section of the horizontal synchronizing signal is used to perform the frame retrieval, etc., of a video signal.</p>
申请公布号 JPH033986(B2) 申请公布日期 1991.01.21
申请号 JP19820080404 申请日期 1982.05.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IMANAKA RYOICHI
分类号 H04N5/92;G11B15/087;G11B20/10;G11B20/12;G11B27/10;G11B27/28;G11B27/30;H04N5/78 主分类号 H04N5/92
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