发明名称 BUS CYCLE RETRIAL SYSTEM
摘要 PURPOSE:To recover the fault of a memory by providing a device to carry out a DMA bus cycle in preference to a retrial bus cycle if a DMA request is produced before the retrial bus cycle is carried out. CONSTITUTION:A DMA request is produced right before the retrial read cycle of a main processor 30 is carried out, and a DMA read cycle is carried out in preference to a retrial read cycle. In this case, a DMA bus occupation signal is outputted with a DMA request given from a DMA processor 40. At the same time, an address is outputted to an address bus 101 and the DMA read cycle is started. Then the DMA bus occupation signal is inputted to an FF 70 via a signal line 104, and the FF 70 is reset. As a result, the new data is latched by a data latch 62 from the processor 40 and the correction data is read out of the latch 62 via a selector 63.
申请公布号 JPH0312761(A) 申请公布日期 1991.01.21
申请号 JP19890147335 申请日期 1989.06.09
申请人 HITACHI LTD;HITACHI COMPUT ENG CORP LTD 发明人 ANDO MASAMICHI;YAMAZAKI KIICHI;KITANO MASAHIRO
分类号 G06F11/14;G06F12/16;G06F13/00;G06F13/30 主分类号 G06F11/14
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