CLOCK GENERATING CIRCUIT FOR DIGITIZING VIDEO SIGNAL

摘要

PURPOSE:To prevent complicated control of circuit and deterioration in the phase adjustment accuracy by selecting an optional phase at a 1/2 step of a period of an output clock of a PLL oscillation circuit and applying phase adjustment of a range of 1/2 period with a delay line. CONSTITUTION:A horizontal synchronizing signal Hs is inputted to a PLL oscillation circuit 1 and an oscillated output synchronized with the input and an output inverted through an inverter 4 are switched by a 1st output selection switch 7 and fed to a 1st frequency divider 2 and a frequency division ratio selector switch 5. The output of the frequency divider 2 is switched by a 2nd output selector switch 8 and fed to the 2nd frequency divider 3 and the switch 5. The output of the frequency divider 3 is switched similarly by a and output selector switch 9 and fed to the succeeding frequency divider and the switch 5. Then the output of the n-th frequency divider N is switched by an m-th output selector switch M and fed to the switch 5. Then the frequency of the output clock is decided by the selection of the switch 5.