| 摘要 |
PURPOSE:To enable the micronization of a unit cell by a method wherein one conductivity type channel region is formed, and then a processing ranging from the processing of a part around a gate to the formation of the connector hole of an electrode is carried out through a single mask using a self-alignment technique. CONSTITUTION:An N-type high resistive single crystal silicon semiconductor layer 25, a silicon oxide film 26, a P-type channel region 27, an N-type source region 28, a silicon nitride film 29, and a silicon oxide film 30 are successively formed on an N-type low resistive single crystal silicon semiconductor substrate 24. Then, the films 30, 29, and 26 are etched to form a U-shaped groove 24a, a silicon oxide film 31 is formed on the side wall of the groove 24a, and a gate oxide film 32 is formed through the film 29 as a mask. A phosphorus doped polycrystalline silicon 33 as a gate electrode is etched back to enable the film 29 to be exposed, a silicon oxide film 34 is formed using the film 29 as a mask, and then the films 29 and 26 are successively removed. Next, a groove 24c is formed so deep as to reach to the region 27 using the film 34 as a mask. Then, an Al 35 and an Al 36 are provided to the substrate 24 so as to serve as a source electrode and a drain electrode respectively. |
