DEMODULATING CLOCK CORRECTION DEVICE

摘要

PURPOSE:To improve a radio data system (RDS) data reception rate and to collect information in a short time by correcting an RDS clock after the demodulation of a received error RDS signal in an RDS receiver. CONSTITUTION:A shift register enable duty ratio control circuit (SREGEN DUTY ratio control circuit) is constituted of a counter (1) 1, a multiplexer (1) 2, a pulse generator (1) 3, a counter (2) 4, a counter (2) 4, a multiplexer (2) 5, and a pulse generator (2) 6, and generates a basic clock synchronously with the received RDS clock and whose pulse width is properly modulated by the duty ratio control. An internal clock generating circuit generates an internal clock based on the basic clock and a demodulates RDS clock. Since the demodulates RDS clock is corrected into an accurate clock as the internal clock, the reception rate of the receiver RDS data after demodulation is improved and the information is collected in a short time.