| 摘要 |
1. A bit by bit time assembling and serialization system in a multiplex of high order and vice-versa of multiplex of packets of low cut into equal and recurrent intervals of time in which the information to be transmitted is cut into packets each packet occupying an interval of time, each interval of time not occupied by a packet comprising a synchronization signal with, among the multiplexes of low order (E1 to En) to be assembled, one of them transmitting a synchronization signal of a first type (CAD1) whilst the others each transmit a synchronization signal of a second type (CAD2), characterised in that the input channels transmitting the multiplexes of low order (E1 to En) are connected to the corresponding inputs of a bit by bit time multiplexer (MUX) the output of which is connected to a bit by bit time demultiplexer (DEMUX) the outputs of which are connected to corresponding output channels (S1 to Sn), each output channel (Sj) being connected in parallel to the input of a detector of synchronization signals (Dj) capable of identifying the synchronization signal of the first type (CAD1) and the synchronization signal of the second type (CAD2) and distinguishing them from one another, the outputs of the detectors (D1 to Dn) being connected to the corresponding inputs of an identity detector coder (COD) transmitting a recognition of a synchronization signal of the first type (CAD1), the output of the coder (COD) being connected to a scanning counter (CEXP) of the demultiplexer (DEMUX) to shift the scanning of the demultiplexer (DEMUX) as a function of the identity of a detector (Dj) having supplied the recognition of a synchronization signal of the first type (CAD1). |
