发明名称 TROUBLE DETECTING CIRCUIT
摘要 PURPOSE:To quickly confirm a faulty RAM and a faulty data bus bit by providing a diagnostic ROM and a decoder which decodes information to select a RAM which is outputted from the diagnostic ROM. CONSTITUTION:When a CPU 4 apparently reads out a diagnostic memory 1, the output of a RAM selecting part 1C is sent through a decoder 2 to successively select RAMs 6 in the system where trouble occurs, and the address to designate the area where test data should be written, from an address storage part 1A, a test data from storage part 1B, and write condition from read/write data part 1D respectively are outputted to these RAMs 6 to store test data. Thereafter, a buffer 10 goes to the diasable state, and a read condition is outputted from the read/write data part 1D, and the CPU 4 reads out test data written in RAMs 6 and compares it with data of a correct answer value in a CS 5. Thus, a faulty part is quickly detected with each bit of a data line as the unit.
申请公布号 JPH0310347(A) 申请公布日期 1991.01.17
申请号 JP19890146386 申请日期 1989.06.07
申请人 NEC IBARAKI LTD 发明人 HOSHINO HIROYUKI
分类号 G06F12/16;G06F11/22 主分类号 G06F12/16
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