发明名称 METHOD AND DEVICE FOR OPTIMIZING ARRANGEMENT AND CIRCUIT DESIGNING DEVICE
摘要 <p>PURPOSE:To obtain an optimum arrangement by calculating a constraint condition variable value until a circuit evaluation function value comes to an optimum value, and also, the constraint condition variable value converges to a constraint condition, then determining an arrangement position of an operation object circuit allocated to a process from a coordinate of the processor. CONSTITUTION:A constraing condition variable value when an i-th (i=1-n) circuit is placed in a k-th (k=1-n) place is calculated by processor of coordinates (i, k) until a circuit evaluation function value comes to an optimum value, and also, the constraint condition variable value converges to a constraint condition, and an arrangement position of an operation object circuit allocated to the processor is determined from the processor by which an output value is converged to the constraint condition and its coordinate. When an output of the processor of the coordinates (i, k) comes to '1' by a fact that the processor of coordinates (i, 1-n) executes this operation, an output of the other processor [i, 1-n (except k)] comes to '0'. In such a way, when an i-th circuit is placed in a place (k), an optimum arrangement is obtained.</p>
申请公布号 JPH0310378(A) 申请公布日期 1991.01.17
申请号 JP19890144123 申请日期 1989.06.08
申请人 HITACHI LTD 发明人 DATE HIROSHI;HAYASHI TERUMINE
分类号 H01L21/82;G06F15/18;G06F17/50;G06F19/00;G06N3/00;G06N3/10;G06Q10/04 主分类号 H01L21/82
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