发明名称 DETECTING CIRCUIT FOR FIXED FAULT IN MEMORY
摘要 PURPOSE:To speedily detect only a fixed fault separately from the error of a software by providing a comparing means to compare the respective address and syndrome of a holding object with the address and syndrome held in preceding time and the holding/informing means of error information. CONSTITUTION:When data are partially written or read and an error, which can be corrected, is generated, comparator circuits 5 and 6 are activated through an AND gate 10. Next, the circuit 5 compares the address from a timing adjusting circuit 1 with the address under holding in an address holding circuit 3 and only when the addresses are coincident, an output is increased to be high. The comparator circuit 6 compares the syndrome from the circuit 1 with the syndrome under holding in a syndrome holding circuit 4 and only when the syndrome is coincident, the output is increased to be high. When the outputs of the circuits 5 and 6 simultaneously rise up to be high, namely, when it is discriminated that the error is continuously generated in the same bit position of the same address, such a state is considered as the fixed fault and the error information are held and notified. Then, only the fixed fault can be speedily detected separately, from the error of the software.
申请公布号 JPH038039(A) 申请公布日期 1991.01.16
申请号 JP19890108905 申请日期 1989.04.27
申请人 NEC CORP 发明人 ISHIKAWA HISASHI
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
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