发明名称 SIGNAL VOLTAGE DIVIDING CIRCUIT
摘要 PURPOSE:To realize a signal voltage dividing circuit of high resistance and high accuracy within an IC, by incorporating plural units of equivalent resistances composed of the switch capacity within an IC and clearing the method of the equivalent combination. CONSTITUTION:The clock signal is applied to either one of the switches 7 and 14 via an inverter 16 in order to open and close these two switches with the phase opposite to each other. A capacity 17 is neglected in terms of a low frequency, and the voltage generated at a terminal 4 is divided by resistances R1 and R2. Thus the capacity 17 has only to hold the preceding voltage when the switches 7 and 14 are connected to the contacts 18 and 21. The voltage can be theoretically reduced at will as long as the time constant defined by the value of the capacity 17 and the value of a load resistance 11 has a sufficiently large range to the clock period. And the voltage division ratio can be decided by the capacity ratio between the capacities 8 and 15.
申请公布号 JPS57184319(A) 申请公布日期 1982.11.13
申请号 JP19810068370 申请日期 1981.05.08
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 FUKUSHIMA ISAO;KUWABARA KAZUMI;NISHIJIMA HIDEO;KOBORI YASUNORI;ITOIGAWA KEIICHI
分类号 H03H7/24;H03H11/24;H03H19/00 主分类号 H03H7/24
代理机构 代理人
主权项
地址