发明名称 Bit field logic operation unit.
摘要 <p>A bit field logic operation unit whioh performs a logic operation accompanied by a masking operation comprises a logic operation part (38), a mask pattern generation part (40), and a bit map operation part (42). All parts are constituted by dynamic circuit constructions where the processes are performed in a preset period and an active period. The preset periods of the logic operation part (38) and the mask pattern generation part (42) are carried out simultaneously, and the active periods of the logic operation part and the mask pattern generation part and the preset period of the bit map operation part (42) are carried out simultaneously.</p>
申请公布号 EP0408464(A2) 申请公布日期 1991.01.16
申请号 EP19900402037 申请日期 1990.07.13
申请人 FUJITSU LIMITED 发明人 SATO, YOSHIYASU;SATO, TAIZO
分类号 G06F7/00;G06F7/76;G06F9/305;G06F9/308 主分类号 G06F7/00
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