DIFFERENTIAL AMPLIFIER CIRCUIT.

摘要

A differential amplifier circuit that compares a potential difference between a first input (Ain) and a second input (Vr) to produce complementary output signals (A &cir& NOt , A). Potential drops of the output signals (A, A) are detected by fixing means that is constituted by n-channel FET's (33, 34) of which the drains are connected to nodes (N3, N4) of a flip-flop circuit (20) and of which the sources are connected to a second potential (Vss), and inverters (31, 32) of which the outputs are connected to the gates of the n-channel FET's (33, 34). Nodes (N3, N4) connected to nodes (N1, N2) that produce output signals (A, A &cir& NOt ) are fixed to the second potential (Vss), in order to increase the speed of operation and to decrease the number of timing control signals (O).