发明名称 CLOCK GENERATING DEVICE
摘要 <p>PURPOSE:To prevent the generation of deterioration of stability against a temperature characteristic of constituting parts and a variance of the characteristic, etc., by constituting the device of a digital circuit. CONSTITUTION:A clock outputted from a voltage control oscillator 4 is received by an A/D converter 2 and the center level of a chrominance signal is converted to digital chrominance signal data so that the most significant bit and other lower bits become '1' and '0', respectively. This chrominance signal data is converted to thinned-out data by thinning it out at the timing of an output of a frequency divider 5 by a thinning-out circuit 6, and thereafter, from this thinned-out data, a phase advance state and a lag state of the clock are detected by an advance phase detector 7 and a lag phase detector 8. Subsequently, a phase error voltage (an output of a pump 12) obtained by inputting the outputs of the detector 7 and the detector 8 to a charge pump 12 by a burst gate pulse applied to a terminal 11 by a gate circuit 9 and 10 is brought to feedback to an oscillator 4. In such a way, the clock whose phase is synchronized with the burst signal is obtained from the oscillator 4.</p>
申请公布号 JPH036196(A) 申请公布日期 1991.01.11
申请号 JP19890140489 申请日期 1989.06.01
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 USUKI NAOJI
分类号 H04N9/44;H04N9/45;H04N11/04;(IPC1-7):H04N11/04 主分类号 H04N9/44
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