发明名称 |
ELECTRONIC COMPONENT PACKAGE |
摘要 |
PURPOSE:To make all signal lines the same in line loss of high frequency signal even if the parts of the signal lines on the surface of a layer member exposed outside of a package are plated by a method wherein the parts of the signal lines concerned are formed equal in overall length. CONSTITUTION:A package 12 is constituted in such a manner that two or more signal lines 16 equal in length are arranged on the upper face of the outermost layer member 101 exposed outside of the package 12 through the lowermost layer member 103 sandwiched inside the layer member 101 through the intermediary of a via fill 14. signal line parts 161 and 162 of required length forming a part of the signal lines 16 are alternately formed on the upper face of the member 101 through the upper face of the member 103. By this setup, even if the line part 161 on the upper face of the member 101 is plated for the improvement in corrosion resistance or bonding, two or more signal lines can be made equal in line loss of high frequency signal. |
申请公布号 |
JPH034555(A) |
申请公布日期 |
1991.01.10 |
申请号 |
JP19890139894 |
申请日期 |
1989.06.01 |
申请人 |
SHINKO ELECTRIC IND CO LTD |
发明人 |
MIYAGAWA FUMIO;TAKENOUCHI TOSHIICHI |
分类号 |
H05K3/46;H01L23/522;H01L23/538 |
主分类号 |
H05K3/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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