| 摘要 |
PURPOSE:To reduce fluctuation in an output frequency even when a reference clock signal whose phase is changed is inputted by controlling the circuit so that the phase of a reference clock signal after a phase change and a phase of the outputted clock signal from a frequency divider are synchronized when the phase change in the reference clock signal is detected. CONSTITUTION:When a reference clock signal S1 is abnormal and the reference clock signal S1 whose phase is shifted by +90 deg. is sent to a phase comparator 9, a counter (1)14 gives no output and since the phase is deviated by T+t2 of above from the usual phase, a counter (2)15 outputs a pulse S13. A pulse width conversion circuit 18 converts the pulse width of a signal S15 of an AND gate 17 to generate a signal S16 whose pulse width is 1/4T, the signal is fed to frequency divider 12, which is cleared. The frequency divider 12 restarts the frequency division when the pulse of the signal S16 is lost and the phase of the output signal S5 is synchronized with the phase of the reference clock signal S1 after the phase change. |
