| 摘要 |
A programmable delay line (1), where the integration capacitor is implemented using the parasitic drain-to-substrate capacitance (108) of a circular reset transistor (107). This transistor layout permits this parasitic capacitance to be made small, while still providing a transistor with low on-state series resistance. To control the delay, the user provides a digital value to a two-part DAC structure to define an equivalent resistance at a pull-down node. The delay line is configured using two identical halves. The output of the two halves is combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not also introduce asymmetry into the output waveform. |
