| 摘要 |
PURPOSE:To attain stable and sufficient DC compensation even in an ultrahigh speed digital communication system by combining a differentiating circuit, a logic circuit and an FF circuit. CONSTITUTION:A differentiating equalizing signal of a binary input signal (a) subjected to DC interrupt is generated by a differentiating circuit 2. A signal subject to DC balance is obtained independently of the mark rate as a waveform of an output signal (b) of the differentiating circuit 2. Then a logic circuit 3 outputs a noninverting signal and an inverting signal of the output signal (b) of the differentiating circuit 2. A set/reset FF circuit 4 receives the noninverting signal (c) as the set pulse and an inverting signal (d) as a reset pulse and outputs an output signal (e) whose DC level is constant independently of the mark rate. |
