| 摘要 |
A parallel data processor is disclosed, in which a plurality of fundamental computing elements each comprising a computer and a memory are connected in a two-dimensional lattice configuration, each of said fundamental computing elements being operated by an identical instruction provided by a single control section, and in which said each fundamental computing element is provided with a shift register having ability of data transmission to the memory in said element and of further data transmission, which is asynchronous to operation in said element, between the adjacent fundamental computing elements, said latter data transmission being conducted concurrently to the operation in said element. |
