| 摘要 |
PURPOSE:To reduce time necessary for a hierarchy expansion processing and realize a high speed processing of cell layout data by a method wherein the cell layout data in the lowest hierarchy are expanded one by one in the order of the layout in accordance with first and second processing to obtain the layout data of all the cells. CONSTITUTION:In accordance with a program wherein the number, which is the maximum number of hierarchies which the hierarchical structure of a ROM cell can take, of respectively subroutines REPEXP1, POLEXP1, MATEXP1 and REPEXP2 which release the hierarchy of one hierarchy defined by single layout, repeated layout or matrix layout are prepared, hierarchy expansion processing corresponding to the maximum number of hierarchies is performed simultaneously. Therefore, time necessary for the hierarchy expansion processing can be substantially reduced and hence a high speed process of cell layout data can be realized. This improvement contributes to the reduction of the lead time of a mask ROM integrated circuit product. |
