发明名称 Level determining circuit generating output signal at first or second output terminal according to level of input signal
摘要 A level determining circuit compares an input signal and a reference signal in level, generates a first output signal at a first output terminal (11) when the former is greater than the latter, and generates a second output signal at a second output terminal (12) if the former is smaller than the latter. A switch (15) is disposed in the preceding stage of the first output terminal, which will be opened if the first output signal is not required. A buffer amplifier portion (14) of high input impedance is further provided in the preceding stage of this switch so that the level determining operation can not be influenced by the change in impedance caused by switching of the switch.
申请公布号 US4983858(A) 申请公布日期 1991.01.08
申请号 US19890404012 申请日期 1989.09.07
申请人 SANYO ELECTRIC CO., LTD. 发明人 ISHIKAWA, TSUTOMU
分类号 G01R29/027;G01R19/165;H03G11/02;H03K5/24;H03K17/30;H04S7/00 主分类号 G01R29/027
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